1. Technical Field of the Invention
The present invention relates to computer memory systems and, more particularly, to a computer memory system with a memory controller that can read or write chunks of data in burst lengths that are shorter than the prefetch length of the corresponding memory.
2. Background Art
Computer systems typically include memory devices from which data may be written to or read from. A commonly used memory device to store relatively large amount of data are dynamic random access memories (DRAMs). Examples of DRAMs include synchronous DRAMs (SDRAMs) and double data rate SDRAMs (DDR DRAMs). A specification for DDR-II DRAMs (a next generation of DDR DRAMs) is being finalized. Other synchronous DRAMs include Rambus RDRAMs. There are various types of memory other than DRAMs including static random access memories (SRAMs). Other types of memory are being developed.
Memory controllers issue write requests and read requests to DRAMs. The memory controller and DRAMs are coupled through a bus that carries write or read data. The data to be stored in response to a write request may originate from a processor or another chip. The data provided by the DRAM in response to a read request may be used by the processor or another chip. The memory controller may be in a physically separate chip from the processor or may be on the same chip as the processor.
A burst length is the number of chunks of data stored in the memory core or retrieved from the memory core in response to a write or read command and a corresponding starting address. Each of the chunks is associated with a full clock cycle in the case of SDRAM and a half clock cycle in the case of double data rate DRAMs, such as DDR and DDR II DRAMs. There are many parallel bits of data in each chunk. The DRAMs have a core prefetch length, which is the number of clock cycles (in the case of SDRAMs) or half cycles (in the case of DDR DRAMs) of data that is either written into or retrieved from the core by a single write or read operation. The term prefetch is used to reference both writing to a memory core and reading from the core.
SDRAM and DDR DRAMs have a controllable burst length and DDR-II DRAMs will have a controllable burst length. However, these memories do not have and are not expected to have controllable core prefetch lengths. SDRAMs have prefetch lengths of 1 clock cycle and allow burst lengths of 1, 2, and 4 clock cycles. Accordingly, if the burst length is 1, there is only one prefetch operation for each write or read command. If the burst length is 2, there are two prefetch operations for each write or read command. If the burst length is 4, there are four prefetch operations for each write or read command. DDR DRAMs have prefetch lengths of 2 half clock cycles and allow burst lengths of 2, 4, and 8 half clock cycles. Accordingly, if the burst length is 2, there is only one prefetch operation for each write or read command. If the burst length is 4, there are two prefetch operations for each write or read command. If the burst length is 8, there are four prefetch operations for each write or read command. DDR-II DRAMS will have burst lengths of 4 and 8 half clock cycles and prefetch lengths of 4 half clock cycles. Accordingly, if the burst length is 4, there is only one prefetch operation for each write or read command. If the burst length is 8, there are two prefetch operations for each write or read command.
It is expected that there will some day be a DRAM with a prefetch length of 8 (this may be a DDR-II DRAM, which currently does not exist). A problem will then occur when a DRAM with a prefetch length of 8 is used in connection with a memory controller that expects burst lengths of 4. The following disclosure presents solutions to this problem.
Memories devices have been used in an interleaved fashion through dynamically controlling output driver enables. A pin has been used to control the output enables of one memory versus another in an interleaved fashion. Memory devices have tri-stated drivers during a read operation or in masking data.